Abstract: With ever-increasing applications comes the realization that efforts and complexity for developing hardware to keep pace with such compute demands are growing at an even faster rate. As the target cadence of Moore's law is already slipping, more burden is placed on the design methodology to achieve “equivalent scaling.” In this talk, Nan will introduce how intelligence is infused to empower hardware agile development and foster the virtuous cycle between hardware and ML. Hardware development involves many evaluation-optimization verification iterations. She will discuss how graph learning and deep reinforcement learning are applied for fast and accurate design evaluation, efficient and scalable design optimization, and high-quality and productive design verification, with the ultimate goal to propel no-human-in-the-loop automation for scalable and efficacious hardware development flow.
Bio: Nan Wu is a Ph.D. candidate in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara, working with Prof. Yuan Xie. Her research interests reside in the joint area of computer architecture, electronic design automation, and machine learning (ML), aiming to facilitate hardware agile development empowered by ML. She received bachelor's degrees in electronic engineering and economics from Tsinghua University in 2016, and a master's degree in electrical and computer engineering from the University of California, Santa Barbara in 2018.
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