Abstract: Modern computer systems deployed at the cloud and the edge provide increased flexibility, cost-effectiveness and data sharing. Most of these systems typically deploy machine learning (ML) algorithms to improve user experience and dedicated hardware to accelerate ML. All these benefits typically come at the expense of security vulnerabilities and reliability concerns. Dr. Potluri's recent focus has been on protecting edge devices like ML accelerators, FPGAs and smartphones from side-channel attacks and workload-based faults. In this talk, he will discuss the world's first scan chain exploits on ML hardware, as well as his work on improving the reliability and fairness in FPGA virtualization. In attacking ReLU networks, he will show how exploiting scan chains combined with small-signal analysis can lead to multiple orders of magnitude reduction, both in queries/accuracy compared to black-box methods. The evaluation of both non-bijective as well as bijective networks will be covered in detail. Coming to FPGA virtualization, the challenges with partial reconfiguration, context switches, task migration, fairness, etc. will be highlighted as well. Finally, an outlook is given on future directions in trustworthy ML, explainable ML for hardware security and well as FPGA virtualization.
Bio: Dr. Seetal Potluri earned his Ph.D. in electrical engineering from the Indian Institute of Technology (IIT) Madras. His current research interests include trustworthy machine learning (ML) systems, scalable and reliable FPGA virtualization, reverse engineering for malware detection in cloud FPGAs, and explainable ML for hardware security. Dr. Potluri is currently working as a post- doctoral research fellow in the electrical and computer engineering department at North Carolina State University and has varied experience in the industry, as well as teaching and research. Dr. Potluri received the best paper recognition award at IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 2022 and his Ph.D. thesis was a runner-up in the IEEE TTTC Doctoral Thesis Contest 2015 (Asia). He has published a number of journal articles, refereed conference papers, and has an approved WIPO patent. Dr. Potluri serves as a member of technical program committees of leading conferences including DAC. He is a member of both IEEE and ACM.
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