Title: Navigating the Confluence: Leverage AI, Confidential Computing, and Heterogeneous Integration
Abstract: Generative design, powered by artificial intelligence (AI) and machine learning, revolutionizes engineering processes. It automates topology optimization, simulation, and concept generation. Things that were once manual and labor intensive are now becoming feasible by AI adapting designs to specific requirements, whether in architecture, design, implementation, verification, manufacturing, or even brainstorming with humans. On the hardware side, heterogeneous integration is revolutionizing the industry by combining diverse components and technologies from electronics and photonics on a single chip, significantly improving performance, power, cost, and innovation in various applications. Hence, the semiconductor industry is undergoing a transformative shift driven by the integration of AI, large language models, and heterogeneous systems. This seminar will explore how AI reshapes the chip design landscape, enabling more intelligent automation, optimization, and prediction across design stages while maintaining reliability, testability, and confidentiality. We will discuss the reliability and security of silicon photonic heterogeneous integration to optimize computing, performance, and efficiency for diverse workloads. Finally, the webinar will address the critical role of confidential computing, specifically, fully homomorphic encryption (FHE), in safeguarding intellectual property and sensitive data in an increasingly complex cloud-based threat environment by utilizing optical network and wafer-scale. Join us in discovering how these technologies are converging to drive innovation and security in the frontier of semiconductors.
About the speaker: Dr. Sazadur Rahman is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida. He is affiliated with both ECE and CS departments at UCF under the “Cyber Security and Privacy Cluster.” Before joining UCF, Dr. Rahman was a Security Architect at Intel Corporation, working in security hardening and threat modeling of next-generation Xeon processors. He earned his Ph.D. and M.Sc. from the Department of Electrical and Computer Engineering, University of Florida at FICS lab. Earlier, Dr. Rahman received a B.Sc. degree in Electrical and Electronic Engineering from the Bangladesh University of Engineering and Technology. Before starting his graduate studies, Dr. Rahman was a design engineer in different fabless semiconductor companies for four years to work on industrial scale 28nm and 14nm custom ICs. He has co-authored over twenty peer-reviewed research papers, four patents, one textbook, and several book chapters. His research works are showcased in premier ACM/IEEE journals and conferences, including the Design Automation Conference (DAC), Design Automation and Test in Europe (DATE), IEEE International Test Conference (ITC), IEEE Hardware Oriented Security and Trust (HOST), Elsevier Integration, and ACM Transactions on Design Automation of Electronic Systems (TODAES). He has been a TPC member for numerous IEEE and ACM conferences including DAC, HOST, GLSVLSI, ICCD, etc. His research interests include Supply Chain Security, Silicon-photonic Heterogeneous Integration, AI-Assured Chip Design, and data privacy.
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