Join us as doctoral candidate Richard Yarnell presents "Meta-Heuristic Optimization Techniques for Convolutional Neural Network Design Space Exploration and Hardware Synthesis."

Abstract: Ubiquitous computing has become the norm in the 21st century. The Internet of Things (IoT) is constantly growing, and intelligent devices pervade all of society. At the same time, machine learning algorithms are becoming more complex, requiring high-powered cutting-edge processors to meet the demands of many simultaneous users. Unfortunately, the ever-expanding IoT and constantly advancing algorithms are at odds with each other. As intelligent computers are introduced into smaller and more widely distributed platforms, constraints such as area, power and latency begin to limit the effectiveness of these devices. To combat this problem, this research introduces tools and meta-heuristics aimed at optimizing a subset of these algorithms, specifically deep neural networks (DNNs) for image classification, to enable their deployment into a variety of fixed-area and power-restricted platforms. First, a workflow utilizing Xilinx Vitis AI is tested on an UltraScale+ field programmable gate array, achieving a top-five accuracy of 0.950 while utilizing less than 25% of the throughput of a machine learning co-processor. Next, a meta-heuristic for the solving of complex multi-objective problems is introduced that is shown to successfully synthesize digital logic circuits. Additionally, a novel science, technology, engineering and mathematics educational tool is introduced to facilitate student learning of DNN architectures and hardware synthesis principles. Finally, DNNs such as VGGNet are synthesized using Xilinx Vitis high-level synthesis over a range of optimization strategies to facilitate targeted improvements and identify system bottlenecks. Building upon this research, this research proposes creation of a new tool, named Hardware-Adaptive Design Exploration and Synthesis (HADES), to perform optimization of DNNs prior to their deployment into IoT devices. The HADES workflow will utilize a novel meta-heuristic to search the DNN design space with the aim of satisfying a diverse set of platform-specific requirements including model accuracy, hardware area, latency and power.

Bio: Richard Yarnell received his bachelor’s and master’s degrees in electrical and computer engineering from Carnegie Mellon University in Pittsburgh, Pennsylvania. He is a doctoral candidate in computer engineering at UCF under the supervision of Ronald DeMara. His research interests include programmable logic design, hardware accelerators and evolutionary computing. He also has more than 20 years of industry experience as a programmable logic designer and is an IEEE senior member.